Future Trends in SOI Devices

This paper discusses the future trends of CMOS devices on SOI wafers in Motorola. Much of the early work dealt with substrate and device development on SIMOX wafers [1, 2]. This kind of work continued as bonded SOI wafers became available [3,4]. When many of the early materials and device issues had been addressed, Motorola manufactured high performance microprocessors on SOI wafers in 2001. Building microprocessors on SOI wafers provided a 15-20% increase in performance over their counterparts on bulk wafers [5]. A future trend in SOI wafers will be thinner Si layers for enhanced device performance at small technologies. While Si thicknesses have been about 1000Å at 130nm and older technologies, the thickness is expected to be around 700Å at the 90nm technology node. A 15-20% improvement in ring oscillator delay is seen by this decrease (Fig. 1). PDSOI requires body-contacted devices to suppress floating body effect. A novel body contact structure was proposed to provide a simple means of eliminating the floating body effect with no impact on performance and minimal added cost [6]. At the 65nm node strained Si devices will be introduced [7]. Silicon Germanium On Insulator SGOI provides high performance through enhanced mobility devices in a thin strained Si layer on relaxed SiGe [8]. We observed extremely high electron mobility enhancements in strained Si devices on bulk wafers (Fig. 2). Given this enhancement on bulk, simulations of devices on SGOI show performance surpassing ITRS high performance and low operating power targets for a physical gate length of 30nm (Fig.3). As the top Si/SiGe layers continue to thin, eventually there will be no room for the SiGe. Another structure, Strained Si On Insulator (SSOI), where the SiGe is removed, may be ready then [9]. At this point, PDSOI devices should be approaching fully depleted (FD) operation. FDSOI and FDSSOI will be used to overcome scaling issues associated with conventional PDSOI devices for high performance and low power, respectively. While FDSSOI substrates are not readily available yet, Motorola has a long history of FDSOI device development with advanced features such as metal gate electrodes [10, 11, 12], elevated extensions [13], and high k gate dielectrics [14]. Simulations of FDSOI devices show that they surpass the ITRS low operating power targets for a physical gate length of 30nm and a Si thickness less than about 3nm (Fig. 4). FDSOI devices are desirable for low-power, low-voltage applications due to low junction capacitance. In addition, this technology can provide improved subthreshold slope, is free from floating body effects, has reduced sensitivity to temperature and Single-Event Upset, and larger immunity to short channel effects. However, several substrate issues remain for ultra-thin SOI. These include shortand long-range non-uniformities, and high densities of pinholes in the Si layer (Fig. 5, 6) [15]. Ultimately, scaling issues will drive the conversion to double-gated devices. Our early work on FinFETs (Fig. 7) is encouraging [16]. SOI wafers provide a convenient substrate for processing these devices providing all the advantages of FDSOI devices. The strengths and weaknesses of the three novel devices can easily be seen in saturated ID-VG curves (Fig. 8). Strained Si devices (SGOI, SSOI, and strained DGFETs) with their enhanced mobilities, Ion, and Ioff should meet high performance targets. FDSOI and FinFETs with their extremely low Ioff and subthreshold slopes should meet the low power targets. Minimization of parasitic resistances will determine the performance level achieved with these devices. The combination of novel structures and SOI substrates will enhance the continued following of Moore’s Law into the near future.